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| Integrated Circuit Systems, Inc. ICS9112A-16 Low Skew Output Buffer General Description The ICS9112A-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz. ICS9112A-16 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112A-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Features * * * * * * * * Zero input - output delay Frequency range 25 - 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC or 173 mil TSSOP package. 3.3V 10% operation Block Diagram Pin Configuration 8 pin SOIC, TSSOP 1337K--08/03/07 ICS9112A-16 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME REF 2 3 TYPE IN OUT OUT PWR OUT PWR Input reference frequency. Buffered clock output Buffered clock output Ground Buffered clock output Power Supply (3.3V) Buffered clock output DESCRIPTION CLK2 CLK13 GND CLK33 VDD CLK4 3 3 OUT OUT CLKOUT Buffered clock output. Internal feedback on this pin Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 1337K--08/03/07 2 ICS9112A-16 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 - 3.6 V, TA = 0 - 70 C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 SYMBOL VIL VIH IIL IIH VOL VOH IDD IDD VIN=0V VIN=VDD IOL = 25mA IOH = 25mA REF = 0 MHz Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 2.4 2.0 19 0.10 0.25 2.9 0.3 30.0 50.0 40.0 50.0 100.0 0.4 TEST CONDITIONS MIN TYP MAX 0.8 UNITS V V A A V V A mA Output High Voltage1 Power Down Supply Current Supply Current Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. All Skew specifications are mesured with a 50 transmission line, load teminated with 50 to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. 1337K--08/03/07 3 ICS9112A-16 Switching Characteristics PARAMETER Output period Input period Duty Cycle1 Duty Cycle1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Output to Output Skew1 Device to Device Skew1 Cycle to Cycle Jitter1 PLL Lock Time1 Jitter ; Absolute Jitter1 Jitter ; 1 - Sigma1 SYMBOL t1 t1 Dt1 Dt2 tr1 tf1 tr1 tf1 Dr1 Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=30pF Measured at 1.4V; CL=30pF Measured at VDD/2 Fout <66.6MHz Measured between 0.8V and 2.0V: CL=30pF Measured between 2.0V and 0.8V; CL=30pF Measured between 0.8V and 2.0V: CL=5pF Measured between 2.0V and 0.8V; CL=5pF Measured at 1.4V All outputs equally loaded, CL=20pF Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66 MHz, loaded outputs Stable power supply, valid clock presented on REF pin @ 10,000 cycles CL=30pF @ 10,000 cycles CL=30pF -100 70 14 0 1 1 0 350 250 700 200 1.0 100 30 MIN 40.00 (25) 40.00 (25) 40.0 45 50 50 1.2 1.2 TYP MAX 7.5 (133) 7.5 (133) 60 55 1.5 1.5 UNITS ns (MHz) ns (MHz) % % ns ns ns ns ps ps ps ps ms ps ps Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of 1.4V 3. All parameters expected with loaded outputs 1337K--08/03/07 4 ICS9112A-16 Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(1-4) outputs loaded equally, with CLKOUT loaded More. REF input and CLK(1_4) outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations 1337K--08/03/07 5 ICS9112A-16 150 mil (Narrow Body) SOIC N C SYMBOL L INDE X ARE A E H 12 D h x 45 A A1 A A1 B C D E e H h L N a VARIATIONS N In Millimeters COMMON DIMENSIONS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 SEE VARIATIONS 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 SEE VARIATIONS .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 SEE VARIATIONS 0 8 D mm. MIN 4.80 MAX 5.00 MIN .1890 D (inch) MAX .1968 e B SEA TING PLANE .10 (.004) 8 Reference Doc.: JEDEC Publication 95, MS-012 10-0030 150 mil (Narrow Body) SOIC Ordering Information ICS9112AM-16LF-T Example: ICS XXXX A M PPP LF-T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M = SOIC Revision Designator Device Type Prefix ICS, AV = Standard Device 1337K--08/03/07 6 ICS9112A-16 N c L E1 INDEX AREA E 12 D In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D SEE VARIATIONS E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS 0 8 aaa -0.10 VARIATIONS In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004 A2 A1 A -Ce b SEA TING PLANE N 8 10-0035 D mm. MIN 2.90 MAX 3.10 MIN .114 D (inch) MAX .122 Reference Doc.: JEDEC Publication 95, MO-153 aaa C 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS9112AG-16LF-T Example: ICS XXXX A G PPP LF-T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator Device Type Prefix ICS, AV = Standard Device 1337K--08/03/07 7 ICS9112A-16 Revision History Rev. H I J K Issue Date 09/01/04 11/02/04 04/26/07 08/03/07 Description Updated Lead Free information Added LN option Removed LN option superceded by LF. Updated Switching Characteristics Rise/Fall time. Page # 6-7 6-7 6-7 4 1337K--08/03/07 8 |
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